module counter_props (
    input logic       clk,
    input logic       rst_n,
    input logic       en,
    input logic [3:0] cnt,
    input logic       ovf
);

//                   
clocking cb @(posedge clk);
   default input #1step output #0;
   input rst_n, en, cnt, ovf;
endclocking

//             
always_ff @(posedge clk) begin
   if (!$past(rst_n)) begin
      if (cnt !== 0 || ovf !== 0)
        $error("Reset assertion failed!");
   end
end

//             
always_ff @(posedge clk) begin
   if ($past(en) && $past(cnt) < 15) begin
      if (cnt !== $past(cnt) + 1)
        $error("Increment assertion failed!");
   end
end

//             
always_ff @(posedge clk) begin
   if ($past(en) && $past(cnt) == 15) begin
      if (cnt !== 0 || ovf !== 1)
        $error("Overflow assertion failed!");
   end
end
endmodule